1. Field of the Invention
The present invention relates to an adaptive equalizer of a recorded information reproducing apparatus for reproducing the recorded information from a recording medium.
2. Description of the Related Art
To correctly read recorded data from a optical disk in which digital data is recorded as a bit sequence, it is necessary to correctly apply an information-reading optical beam applied on the disk onto bits.
However, if an optical disk 1 is distorted, it may be set with a tilt in the read direction of a pickup 3 (hereafter referred to as tangential skew) as shown in FIG. 1A or 1B.
Therefore, an information read beam emitted from the pickup 3 is tilted with respect to the disk surface. In this case, a wave front aberration mainly consisting of a coma aberration increases and the waveform of a read signal is distorted.
Therefore, a recorded information reproducing apparatus for reproducing the recorded information from the optical disk is provided with an adaptive equalizer using an FIR (finite impulse response) filter in order to electrically equalize the distorted waveform of the read signal to an ideal waveform.
FIG. 2 is an illustration showing the structure of the adaptive equalizer.
In FIG. 2, a read sample obtained by sampling a read signal read from an unillustrated optical disk is supplied to a system comprising n cascade-connected unit delay elements D.sub.1 to D.sub.n. The unit delay elements D.sub.1 to D.sub.n provide a time delay equal to the sampling cycle of the read sample and the output of one unit delay element serves as an input one sampling period before. The read sample and the output of each unit delay element are supplied to an adaptive arithmetic circuit comprising coefficient multipliers M.sub.0 to M.sub.n, coefficient control circuits C.sub.0 to C.sub.n, and an adder A. Each of the coefficient control circuits C.sub.0 to C.sub.n comprises a multiplier and an integrator. For example, a multiplier m.sub.0 of the coefficient control circuit C.sub.0 supplies a value obtained by multiplying the value of a supplied read sample by an error value obtained by a subtracter S to an integrator i.sub.0. The integrator io supplies a value obtained by averaging the multiplied value to the coefficient multiplier M.sub.0 as a multiplication coefficient. According to the above structure, the respective coefficient control circuits C.sub.0 to C.sub.n update the multiplication coefficients to be supplied to the coefficient multipliers M.sub.0 to M.sub.n so that the error value obtained by the subtracter S may be 0.
The coefficient multiplier M.sub.0 supplies a multiplication result obtained by multiplying the read sample by a multiplication coefficient supplied from the coefficient control circuit C.sub.0 to the adder A. The coefficient multipliers M.sub.1 to M.sub.n multiply values output from the unit delay elements D.sub.1 to D.sub.n by values supplied from the coefficient control circuits C.sub.1 to C.sub.n and supply multiplication results to the adder A, respectively. The adder A computes the sum total of the multiplication results of the coefficient multipliers M.sub.0 to M.sub.n and outputs the sum total as an equalized read sample serving as an output of the adaptive equalizer. The equalized read sample is also led to the subtracter S. The subtracter S computes the difference between the equalized read sample and a reference value and supplies the difference value to the coefficient control circuits C.sub.0 to C.sub.n as the error value described above. The reference value supplied to the subtracter S is set to a value for bringing the overall transfer characteristic in the adaptive equalizer and its input system into an ideal or a desired transfer characteristic.
As described above, the adaptive equalizer equalizes the waveform of the read signal to an ideal waveform which ought to be by updating each filter coefficient of the FIR filter at all times.
However, an adaptive equalizer having the structure shown in FIG. 2 has a problem that the circuit scale is increased because the adaptive equalizer requires numbers of coefficient control circuits C.sub.0 to C.sub.n and coefficient multipliers M.sub.0 to M.sub.n corresponding to the number of the unit delay elements D.sub.1 to D.sub.n.